1. Field of the Invention
The present invention relates to the setting of flag signals which indicate the status of a device such as an first-in first-out buffer.
2. Description of Related Art
A first-in first-out (FIFO) buffer often is useful between devices with different clock frequencies. In typical operation of a FIFO, a first device, such as micro-processor writes to the FIFO buffer and a second device, such as a peripheral or a second microprocessor, reads from the FIFO buffer. Each device reads or writes according to its own clock. Because two different clocks control the timing of read and write operations, the buffer handles the operations asynchronously, and the devices may write then read with a very short time separation.
To maximize data flow the FIFO buffer must be ready to respond to the next operation quickly. Any processing time required between one operation and a subsequent operation can delay the subsequent operation and slow the rate of data flow through the buffer. In particular, the time that the buffer takes to recalculate status flags after an action by one processor tends to slows down the buffer.
FIG. 1 show a typical application of a FIFO buffer 103. The FIFO buffer 103 holds data that is written to the buffer 103 by a first device 101 and read from the buffer 103 by a second device 102. Besides holding the data, the buffer 103 sends flag signals to the attached devices 101 and 102. For example the buffer 103 could send a full signal to the first device on a flag line 106 when the buffer is full, or could send an empty signal to the second device 102 on line 107 when the buffer is empty.
When the first device 101 has data to write to the buffer 103, the first device 101 checks for the full flag signal on line 106. If the flag signal indicates the buffer 103 is full the first device 101 must wait before sending data to buffer 103. If the buffer 103 is not full the first device 101 asserts data signals to the data lines 104 and sends a write clock or control signal to the buffer 103 on a line 108. The buffer 103 stores the data in a memory location pointed to by a write pointer and then increments the write pointer.
When data is in the buffer 103 the buffer 103 clears the empty signal on line 107, which indicates to the second device 102 that data is available to be read from the buffer 103. The second device 102 sends a clock or control signal to the buffer 103 on line 109, and the buffer 103 asserts to data lines 105 the data pointed to by a read pointer. After the second device 102 reads the data, the buffer 103 increments the read pointer.
With this architecture if the read pointer and the write pointer point to the same location then the FIFO buffer is either empty or full. It is full if enough data has been written so that the write pointer has just incremented to equal the read pointer. It is empty if the read pointer has just incremented to equal the write pointer. The FIFO buffer needs to signal these two conditions to the devices connected to the buffer.
When the two devices connected to a FIFO buffer do not have synchronized clocks, reads and writes to the buffer occur asynchronously, so the read pointer and write pointer change asynchronously. Still, when one of the devices connected to the buffer takes an action, the various status flags need to be changed to reflect the new values of the pointers. The devices connected to the buffer either wait while the new flags are calculated or take actions based on incorrect flags. The speed of the FIFO buffer, therefore, may be limited by the speed of flag output. If the speed of the flag output is improved then the speed of the FIFO can be improved.
In a FIFO buffer, flag output is normally generated from the values of the two pointers. For example, immediately after a device writes data to the buffer the read pointer may point to location i and the write pointer may point to location j. The full flag needs to be activated if the two pointers point to the same location, i.e. i=j. In typical prior art architecture, the FIFO buffer would compare the two pointer values and generate the flag signal for the connected device to act on. The connected devices normally have to wait the time it takes a comparator to generate the flag signal. Accordingly, a need exists to reduce or eliminate this wait and thereby speed up the operation of the system including the FIFO buffer.